? semiconductor components industries, llc, 2011 april, 2011 ? rev. 7 1 publication order number: ntd4806n/d ntd4806n power mosfet 30 v, 76 a, single n ? channel, dpak/ipak features ? low r ds(on) to minimize conduction losses ? low capacitance to minimize driver losses ? optimized gate charge to minimize switching losses ? these are pb ? free devices applications ? cpu power delivery ? dc ? dc converters ? low side switching maximum ratings (t j = 25 c unless otherwise noted) parameter symbol value unit drain ? to ? source voltage v dss 30 v gate ? to ? source voltage v gs 20 v continuous drain current (r ja ) (note 1) steady state t a = 25 c i d 14 a t a = 85 c 11 power dissipation (r ja ) (note 1) t a = 25 c p d 2.14 w continuous drain current (r ja ) (note 2) t a = 25 c i d 11 a t a = 85 c 8.8 power dissipation (r ja ) (note 2) t a = 25 c p d 1.33 w continuous drain current (r jc ) (note 1) t c = 25 c i d 76 a t c = 85 c 59 power dissipation (r jc ) (note 1) t c = 25 c p d 60 w pulsed drain current t p =10 s t a = 25 c i dm 150 a current limited by package t a = 25 c i dmaxpkg 45 a operating junction and storage temperature t j , t stg ? 55 to 175 c source current (body diode) i s 50 a drain to source dv/dt dv/dt 6.0 v/ns single pulse drain ? to ? source avalanche energy (v dd = 24 v, v gs = 10 v, l = 1.0 mh, i l(pk) = 21 a, r g = 25 ) e as 220 mj lead temperature for soldering purposes (1/8 from case for 10 s) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. case 369aa dpak (bent lead) style 2 marking diagrams & pin assignments case 369d ipak (straight lead dpak) 30 v 6.0 m @ 10 v r ds(on) max 76 a i d max v (br)dss 9.4 m @ 4.5 v http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. ordering information 1 2 3 4 case 369ad ipak (straight lead) 1 2 3 4 n ? channel d s g yww 48 06ng 1 gate 2 drain 3 source 4 drain 4 drain 2 drain 1 gate 3 source 4 drain 2 drain 1 gate 3 source yww 48 06ng yww 48 06ng y = year ww = work week 4806n = device code g = pb ? free package 1 2 3 4
ntd4806n http://onsemi.com 2 thermal resistance maximum ratings parameter symbol value unit junction ? to ? case (drain) r jc 2.5 c/w junction ? to ? tab (drain) r jc ? tab 3.5 junction ? to ? ambient ? steady state (note 1) r ja 70 junction ? to ? ambient ? steady state (note 2) r ja 113 1. surface ? mounted on fr4 board using 1 in sq pad size, 1 oz cu. 2. surface ? mounted on fr4 board using the minimum recommended pad size. electrical characteristics (t j = 25 c unless otherwise noted) parameter symbol test condition min typ max unit off characteristics drain ? to ? source breakdown voltage v (br)dss v gs = 0 v, i d = 250 a 30 v drain ? to ? source breakdown voltage temperature coefficient v (br)dss /t j 27 mv/ c zero gate voltage drain current i dss v gs = 0 v, v ds = 24 v t j = 25 c 1.0 a t j = 125 c 10 gate ? to ? source leakage current i gss v ds = 0 v, v gs = 20 v 100 na on characteristics (note 3) gate threshold voltage v gs(th) v gs = v ds , i d = 250 a 1.5 2.5 v negative threshold temperature coefficient v gs(th) /t j 6.0 mv/ c drain ? to ? source on resistance r ds(on) v gs = 10 to 11.5 v i d = 30 a 4.9 6.0 m i d = 15 a 4.8 v gs = 4.5 v i d = 30 a 7.9 9.4 i d = 15 a 7.5 forward transconductance gfs v ds = 15 v, i d = 15 a 14 s charges and capacitances input capacitance c iss v gs = 0 v, f = 1.0 mhz, v ds = 12 v 2142 pf output capacitance c oss 480 reverse transfer capacitance c rss 251 total gate charge q g(tot) v gs = 4.5 v, v ds = 15 v, i d = 30 a 15 23 nc threshold gate charge q g(th) 3.0 gate ? to ? source charge q gs 7.0 gate ? to ? drain charge q gd 7.0 total gate charge q g(tot) v gs = 11.5 v, v ds = 15 v, i d = 30 a 37 nc switching characteristics (note 4) turn ? on delay time t d(on) v gs = 4.5 v, v ds = 15 v, i d = 15 a, r g = 3.0 13.9 ns rise time t r 29.7 turn ? off delay time t d(off) 18.3 fall time t f 7.8 turn ? on delay time t d(on) v gs = 11.5 v, v ds = 15 v, i d = 15 a, r g = 3.0 8.5 ns rise time t r 23.8 turn ? off delay time t d(off) 26 fall time t f 4.7 3. pulse test: pulse width 300 s, duty cycle 2%. 4. switching characteristics are independent of operating junction temperatures.
ntd4806n http://onsemi.com 3 electrical characteristics (t j = 25 c unless otherwise noted) parameter symbol test condition min typ max unit drain ? source diode characteristics forward diode voltage v sd v gs = 0 v, i s = 30 a t j = 25 c 0.9 1.2 v t j = 125 c 0.8 reverse recovery time t rr v gs = 0 v, dis/dt= 100 a/ s, i s = 30 a 26 ns charge time ta 13 discharge time tb 13 reverse recovery time q rr 16 nc package parasitic values source inductance l s t a = 25 c 2.49 nh drain inductance, dpak l d 0.0164 drain inductance, ipak l d 1.88 gate inductance l g 3.46 gate resistance r g 1.0
ntd4806n http://onsemi.com 4 typical performance curves 4 v 10 v 50 0.015 60 0.005 0 90 1.5 1.0 0.5 0 10,000 100,000 05 30 2 1 v ds , drain ? to ? source voltage (volts) i d , drain current (amps) 0 v gs , gate ? to ? source voltage (volts) figure 1. on ? region characteristics figure 2. transfer characteristics i d , drain current (amps) 3 0.048 4 0.023 0.013 0.003 5 figure 3. on ? resistance vs. gate ? to ? source voltage v gs , gate ? to ? source voltage (volts) figure 4. on ? resistance vs. drain current and gate voltage i d , drain current (amps) r ds(on) , drain ? to ? source resistance ( ) r ds(on) , drain ? to ? source resistance ( ) figure 5. on ? resistance variation with temperature t j , junction temperature ( c) figure 6. drain ? to ? source leakage current vs. drain voltage v ds , drain ? to ? source voltage (volts) r ds(on) , drain ? to ? source resistance (normalized) i dss , leakage (na) ? 50 50 25 0 ? 25 75 125 100 23 15 10 25 5 3 v ds 10 v t j = 25 c t j = ? 55 c t j = 125 c v gs = 4.5 v 175 v gs = 0 v i d = 30 a v gs = 10 v 50 t j = 175 c t j = 125 c 40 0 160 80 45 t j = 25 c 20 10 5 v 3.2 v 6 v 2.0 6 1000 4 90 1 0 120 610 0.033 70 0.010 80 4.2 v 4.5 v 3.4 v 3.6 v 3.8 v 100 40 10 20 60 80 70 30 150 70 110 20 140 60 100 10 130 50 90 i d = 30 a t j = 25 c 789 0.008 0.018 0.028 0.043 0.038 55 65 75 85 v gs = 11.5 v 150 100
ntd4806n http://onsemi.com 5 typical performance curves c rss 10 0 10 15 25 gate ? to ? source or drain ? to ? source voltage (volts) c, capacitance (pf) figure 7. capacitance variation 1000 0 v gs v ds 2000 55 v gs = 0 v v ds = 0 v t j = 25 c c iss c oss c rss c iss 3000 4000 v gs figure 8. gate ? to ? source and drain ? to ? source voltage vs. total charge v gs , gate ? to ? source voltage (volts) 0 2 0 q g , total gate charge (nc) 8 4 10 5 i d = 30 a v gs = 4.5 v t j = 25 c q 2 q 1 q t 20 15 0 0.5 v sd , source ? to ? drain voltage (volts) i s , source current (amps) figure 9. resistive switching time variation vs. gate resistance r g , gate resistance (ohms) 1 10 100 1000 1 t, time (ns) v gs = 0 v figure 10. diode forward voltage vs. current 100 0.6 0.7 1.0 5 10 15 t r t d(off) t d(on) t f 10 v dd = 15 v i d = 30 a v gs = 11.5 v 0.8 0.9 20 30 25 t j = 25 c figure 11. maximum rated forward biased safe operating area 0.1 1 100 v ds , drain ? to ? source voltage (volts) 0.1 1000 i d , drain current (amps) r ds(on) limit thermal limit package limit 10 10 v gs = 20 v single pulse t c = 25 c 1 ms 100 s 10 ms dc 10 s 20 6 1 100 0 25 t j , junction temperature ( c) i d = 21 a figure 12. maximum avalanche energy vs. starting junction temperature 50 75 175 50 100 150 100 125 200 250 eas, single pulse drain ? to ? source avalanche energy (mj) 150
ntd4806n http://onsemi.com 6 typical performance curves figure 13. avalanche characteristics 1000 1 100 pulse width ( s) i d , drain current (amps) 10 10 125 c 1 100 100 c 25 c figure 14. thermal response r(t), effective transient thermal resistance (normalized) t, time ( s) 0.1 1.0 0.01 0.1 0.2 0.02 d = 0.5 0.05 0.01 single pulse r jc (t) = r(t) r jc d curves apply for power pulse train shown read time at t 1 t j(pk) ? t c = p (pk) r jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 1.0e+00 1.0e+01 1.0e-01 1.0e-02 1.0e-03 1.0e-04 1.0e-05 ordering information order number package shipping ? ntd4806nt4g dpak (pb ? free) 2500 tape & reel ntd4806n ? 1g ipak (pb ? free) 75 units/rail ntd4806n ? 35g ipak trimmed lead (3.5 0.15 mm) (pb ? free) 75 units/rail ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ntd4806n http://onsemi.com 7 package dimensions dpak (single guage) case 369aa ? 01 issue b b d e b3 l3 l4 b2 e m 0.005 (0.13) c c2 a c c z dim min max min max millimeters inches d 0.235 0.245 5.97 6.22 e 0.250 0.265 6.35 6.73 a 0.086 0.094 2.18 2.38 b 0.025 0.035 0.63 0.89 c2 0.018 0.024 0.46 0.61 b2 0.030 0.045 0.76 1.14 c 0.018 0.024 0.46 0.61 e 0.090 bsc 2.29 bsc b3 0.180 0.215 4.57 5.46 l4 ??? 0.040 ??? 1.01 l 0.055 0.070 1.40 1.78 l3 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. thermal pad contour optional within di- mensions b3, l3 and z. 4. dimensions d and e do not include mold flash, protrusions, or burrs. mold flash, protrusions, or gate burrs shall not exceed 0.006 inches per side. 5. dimensions d and e are determined at the outermost extremes of the plastic body. 6. datums a and b are determined at datum plane h. 12 3 4 h 0.370 0.410 9.40 10.41 a1 0.000 0.005 0.00 0.13 l1 0.108 ref 2.74 ref l2 0.020 bsc 0.51 bsc a1 h detail a seating plane a b c l1 l h l2 gauge plane detail a rotated 90 cw style 2: pin 1. gate 2. drain 3. source 4. drain 5.80 0.228 2.58 0.102 1.60 0.063 6.20 0.244 3.00 0.118 6.17 0.243 mm inches scale 3:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
ntd4806n http://onsemi.com 8 package dimensions ipak (straight lead dpak) case 369d ? 01 issue b style 2: pin 1. gate 2. drain 3. source 4. drain 123 4 v s a k ? t ? seating plane r b f g d 3 pl m 0.13 (0.005) t c e j h dim min max min max millimeters inches a 0.235 0.245 5.97 6.35 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.018 0.023 0.46 0.58 f 0.037 0.045 0.94 1.14 g 0.090 bsc 2.29 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.350 0.380 8.89 9.65 r 0.180 0.215 4.45 5.45 s 0.025 0.040 0.63 1.01 v 0.035 0.050 0.89 1.27 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. z z 0.155 ??? 3.93 ??? 3.5 mm ipak, straight lead case 369ad ? 01 issue o b d l e e3 l2 b1 e 3x a1 a a1 a2 dim min max millimeters a 2.19 2.38 a1 0.46 0.60 a2 0.87 1.10 b 0.69 0.89 b1 0.77 1.10 d 5.97 6.22 e 2.28 bsc d2 4.80 ??? e 6.35 6.73 e2 4.70 ??? e3 4.45 5.46 l 3.40 3.60 l1 ??? 2.10 notes: 1.. dimensioning and tolerancing per asme y14.5m, 1994. 2.. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from terminal tip. 4. dimensions d and e do not include mold gate or mold flash. t seating d2 e2 optional construction plane l1 l2 0.89 1.27 2x m 0.13 t d2 e2 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ntd4806n/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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